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d a t a sh eet product speci?cation supersedes data of 1999 may 17 file under integrated circuits, ic18 1999 jun 04 integrated circuits SAA1575HL global positioning system (gps) baseband processor
1999 jun 04 2 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 overview 7.2 the 80c51xa processor 7.3 the gps correlators 7.4 memory organization 7.4.1 data memory space 7.4.2 code memory space 7.5 cpu peripheral features 7.5.1 timers/counters 7.5.2 watchdog timer 7.5.3 uarts 7.5.4 rf ic programming port 7.5.5 general purpose i/o 7.6 the real-time clock 7.7 the external bus 7.7.1 program memory chip select 7.7.2 data memory chip select 7.7.3 read strobe 7.7.4 write low byte strobe 7.7.5 write high byte strobe 7.8 backup supplies and reset 7.8.1 supply domains 7.8.2 power-down design strategy 7.8.3 system reset control 7.8.4 power saving modes 7.9 clock signals and oscillators 7.9.1 system clock (xtal1) 7.9.2 rtc clock (xtal3) 7.9.3 reference clock (rclk) 8 limiting values 9 thermal characteristics 10 dc characteristics 11 ac characteristics 12 default application and demonstration board 13 package outline 14 soldering 14.1 introduction to soldering surface mount packages 14.2 reflow soldering 14.3 wave soldering 14.4 manual soldering 14.5 suitability of surface mount ic packages for wave and reflow soldering methods 15 definitions 16 life support applications
1999 jun 04 3 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 1 features single-chip gps baseband solution with built-in 16-bit microcontroller all digital, 0.5 micron cmos technology single power supply with full 3 v operation separate i/o power supply pins for operation with 3 or 5 v external devices up to 30 mhz system clock from on-chip crystal oscillator or external clock input 2 kbytes words internal data memory for fast execution external bus for up to 512 kbytes words data memory and 512 kbytes words program memory programmable external bus timing to match external memory speed chip selection outputs to reduce glue logic requirements reset controller for power-down detection and servicing 8 gps channel correlators driven by firmware for flexible gps correlation algorithms 1 second pulse output of gps time 2-bit digital if gps signal input synchronized to external sample clock 2 fully duplex uarts for communication with host system processor and other devices real-time clock with 32.768 khz crystal and supply for low power timekeeping watchdog timer power-down modes under firmware control 100-pin lqfp package 50 ma supply current (typ.) when 8 gps channels in track (approximate). 2 general description the SAA1575HL is an integrated circuit which implements a complete baseband function for global positioning system (gps) receivers. it combines a 16-bit philips 80c51xa microcontroller, 8 gps channel correlators and related peripherals in a single ic. users can implement a complete gps receiver using only the SAA1575HL, the uaa1570hl front-end philips ic (or similar), external memory and a few discrete components. the ic is aimed at low cost applications. a low power solution was also used where possible, although this was of secondary importance to cost. the core of the SAA1575HL operates at 3 v. however, for compatibility with current automotive applications, the periphery is supplied from separate pins and can be operated between 3 and 5 v, as required. the function of the SAA1575HL is to read the 1 or 2-bit sampled if bitstream from a front-end ic and, under control of firmware on an external rom, calculate the full gps solution. the results are communicated to a host in national maritime electronics association (nmea) format via a standard serial port. a second serial port can be used to provide differential gps information to the processor for more advance applications. in addition, various other functions are integrated onto the ic such as a real-time gps clock, a power-down/reset controller, timer/counters and a watchdog timer. to summarise, the SAA1575HL has the following functional units: 16-bit 80c51xa microcontroller core 2 kbytes words on-chip sram (16-bit words) 8 gps channel correlators 2 uarts 8 general purpose i/o lines 3 timer/counters 1 real-time clock 1 watchdog timer 1 power-down/reset controller. the structure is based on a 16-bit microcontroller core operating on all other units as memory mapped peripherals and registers. a 16-bit data bus and a 19-bit address bus are extended to external pins so that external data and program memory can be accessed. on-chip decoder circuits eliminate the need for external glue logic for external memory access. each of the 8 gps channel correlators includes a carrier numerically controlled oscillator (nco), pn code generator, phase rotator and low-pass filter. they correlate the local pn sequence with the digitized input gps signal and generate the filtered correlation result for the microcontroller. the firmware provided then generates a navigation solution and provides standard gps data outputs to the user.
1999 jun 04 4 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL the gps firmware is located in off-chip program memory. it processes the gps signals from up to 8 satellites and generates gps information that can be output to the host processor through one of the two serial ports. much of hardware configuration of the SAA1575HL can be controlled by the firmware and so details such as the external bus timing may change between firmware revisions. for the purpose of this document, the standard philips firmware has been assumed (release hd00). 3 quick reference data 4 ordering information symbol parameter conditions min. typ. max. unit v cc(core) core supply voltage 2.7 3.3 3.6 v v cc(p) peripheral supply voltage 2.7 5.0 5.5 v v cc(r) real-time clock core supply voltage 2.4 3.3 3.6 v v cc(b) backup peripheral supply voltage 2.7 5.0 5.5 v i cc(core) core supply current normal mode - 35 - ma sleep mode - 15 - ma i cc(r) real-time clock core supply current f rtc = 32.768 khz - 10 30 m a i cc(b) backup peripheral supply current normal mode; dependent on load - 5 - ma sleep mode - 1 -m a i cc(p) peripheral supply current normal mode - 20 - ma sleep mode -- 1ma f osc oscillator frequency 26 30 32 mhz t amb ambient temperature - 40 +25 +85 c type number package name description version SAA1575HL lqfp100 plastic low pro?le quad ?at package; 100 leads; body 14 14 1.4 mm sot407-1
1999 jun 04 5 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 5 block diagram fig.1 block diagram. mhb460 handbook, full pagewidth uart 0 uart 1 timer 0, 1 80c51xa core SAA1575HL 80c51xa processor module external bus interface timer 2 watchdog timer address and data static ram (2 kbytes words) system clock generator 14 48, 49, 53 to 59, 62 to 64, 67 to 70 15 2 100 93 92 98 99 8, 9 97 72 80 12, 30, 66 16, 25, 37, 51, 61, 86 13, 17, 26, 31, 38, 50, 60, 65, 71, 79, 85 4 34244 1 45 46 47 83 81 84 82 control registers correlators 89 90 91 5 to 7, 87, 88, 94 to 96 real-time clock channel 7 channel 6 channel 5 channel 4 channel 3 channel 2 channel 1 channel 0 control 76 75 reset controller 74 78 52 43 77 10, 11, 18 to 24, 27 to 29, 32 to 36, 39, 40 41 73 sclk t1s test2 test1 rclk n.c. gpio7 to gpio0 a19 to a1 if1 if2 pmcs tp2 rstime tp1 d15 to d0 v ss v cc(p) v cc(r) v cc(b) wrh wrl rd xtal1 xtal2 tp3 tp4 v cc(core) pwrm pwrb xtal3 rxd0 txd0 rxd1 txd1 rfle rfclk rfdat pwrdn xtal4 pwrfail dmcs
1999 jun 04 6 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 6 pinning symbol pin i/o description sclk 1 o sample clock : sample clock generated internally by dividing down the rclk (reference clock) input. this output is provided for use by the front-end ic. t1s 2 o gps time pulse : a 1 pulse per second output whose rising or falling edge (?rmware controlled) is synchronized to gps time when the receiver is tracking a gps signal. the pulse length is approximately 1 ms. tp3 3 i test pin : tie high tp4 4 i test pin : tie high gpio5 5 i/o gpio bit 5 : standard general purpose i/o mapped into the segment 15 of the address space. the top 4 bits can be used as the xa external timer control access pins (t0, t1, t2 and t2ex). gpio6 6 i/o gpio bit 6 : standard general purpose i/o mapped into the segment 15 of the address space. the top 4 bits can be used as the xa external timer control access pins (t0, t1, t2 and t2ex). gpio7 7 i/o gpio bit 7 : standard general purpose i/o mapped into the segment 15 of the address space. the top 4 bits can be used as the xa external timer control access pins (t0, t1, t2 and t2ex). n.c. 8 o not connected : do not connect n.c. 9 o not connected : do not connect a19 10 o external memory address bus bit 19 : 19-bit address bus; used to address external ram and program memory a18 11 o external memory address bus bit 18 : 19-bit address bus; used to address external ram and program memory v cc(core) 12 - main core power supply : 2.7 to 3.6 v only; main supply for the core in normal operation v ss 13 - ground : 0 v reference xtal1 14 i crystal 1 : input to the inverting ampli?er; used in the system oscillator circuit and input to the internal clock generator circuits xtal2 15 o crystal 2 : output from the system oscillator ampli?er v cc(p) 16 - main i/o power supply : 2.7 to 5.5 v operating range; main supply for the periphery in normal operation v ss 17 - ground : 0 v reference a17 18 o external memory address bus bit 17 : 19-bit address bus; used to address external ram and program memory a16 19 o external memory address bus bit 16 : 19-bit address bus; used to address external ram and program memory a15 20 o external memory address bus bit 15 : 19-bit address bus; used to address external ram and program memory a14 21 o external memory address bus bit 14 : 19-bit address bus; used to address external ram and program memory a13 22 o external memory address bus bit 13 : 19-bit address bus; used to address external ram and program memory a12 23 o external memory address bus bit 12 : 19-bit address bus; used to address external ram and program memory
1999 jun 04 7 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL a11 24 o external memory address bus bit 11 : 19-bit address bus; used to address external ram and program memory v cc(p) 25 - main i/o power supply : 2.7 to 5.5 v operating range; main supply for the periphery in normal operation v ss 26 - ground : 0 v reference a10 27 o external memory address bus bit 10 : 19-bit address bus; used to address external ram and program memory a9 28 o external memory address bus bit 9 : 19-bit address bus; used to address external ram and program memory a8 29 o external memory address bus bit 8 : 19-bit address bus; used to address external ram and program memory v cc(core) 30 - main core power supply : 2.7 to 3.6 v only; main supply for the core in normal operation v ss 31 - ground : 0 v reference a7 32 o external memory address bus bit 7 : 19-bit address bus; used to address external ram and program memory a6 33 o external memory address bus bit 6 : 19-bit address bus; used to address external ram and program memory a5 34 o external memory address bus bit 5 : 19-bit address bus; used to address external ram and program memory a4 35 o external memory address bus bit 4 : 19-bit address bus; used to address external ram and program memory a3 36 o external memory address bus bit 3 : 19-bit address bus; used to address external ram and program memory v cc(p) 37 - main i/o power supply : 2.7 to 5.5 v operating range; main supply for the periphery in normal operation v ss 38 - ground : 0 v reference a2 39 o external memory address bus bit 2 : 19-bit address bus; used to address external ram and program memory a1 40 o external memory address bus bit 1 : 19-bit address bus; used to address external ram and program memory pmcs 41 o external program memory select : external program memory read strobe tp2 42 i test pin : tie low rstime 43 i reset timer control : this controls the on-chip reset timer. if this is high, reset will be de-asserted approximately 10 ms after both pwrdn and pwrf ail go high. if this is low, reset will be de-asserted approximately 10 m s after both pwrdn and pwrf ail go high. tp1 44 i test pin : tie low wrh 45 i/o write msb : write strobe for external data memory; asserted for both msb and word write operations; input mode only used for test purposes wrl 46 i/o write lsb : write strobe for external data memory; asserted for both lsb and word write operations; input mode only used for test purposes rd 47 i/o external data read : read strobe for external data memory; input mode only used for test purposes symbol pin i/o description
1999 jun 04 8 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL d15 48 i/o external memory data bus : 16-bit data bus; used to connect to external ram and program memory d14 49 i/o external memory data bus bit 14 : 16-bit data bus; used to connect to external ram and program memory v ss 50 - ground : 0 v reference v cc(p) 51 - main i/o power supply : 2.7 to 5.5 v operating range; main supply for the periphery in normal operation pwrdn 52 i power-down indicator : a low on this pin asserts an xa interrupt intended for use as a power fail interrupt. once reset is asserted, either by pwrf ail or the ?rmware, it will remain asserted until a set time after this pin goes high. d13 53 i/o external memory data bus bit 13 : 16-bit data bus; used to connect to external ram and program memory d12 54 i/o external memory data bus bit 12 : 16-bit data bus; used to connect to external ram and program memory d11 55 i/o external memory data bus bit 11 : 16-bit data bus; used to connect to external ram and program memory d10 56 i/o external memory data bus bit 10 : 16-bit data bus; used to connect to external ram and program memory d9 57 i/o external memory data bus bit 9 : 16-bit data bus; used to connect to external ram and program memory d8 58 i/o external memory data bus bit 8 : 16-bit data bus; used to connect to external ram and program memory d7 59 i/o external memory data bus bit 7 : 16-bit data bus; used to connect to external ram and program memory v ss 60 - ground : 0 v reference v cc(p) 61 - main i/o power supply : 2.7 to 5.5 v operating range; main supply for the periphery in normal operation d6 62 i/o external memory data bus bit 6 : 16-bit data bus; used to connect to external ram and program memory d5 63 i/o external memory data bus bit 5 : 16-bit data bus; used to connect to external ram and program memory d4 64 i/o external memory data bus bit 4 : 16-bit data bus; used to connect to external ram and program memory v ss 65 - ground : 0 v reference v cc(core) 66 - main core power supply : 2.7 to 3.6 v only; main supply for the core in normal operation d3 67 i/o external memory data bus bit 3 : 16-bit data bus; used to connect to external ram and program memory d2 68 i/o external memory data bus bit 2 : 16-bit data bus; used to connect to external ram and program memory d1 69 i/o external memory data bus bit 1 : 16-bit data bus; used to connect to external ram and program memory d0 70 i/o external memory data bus bit 0 : 16-bit data bus; used to connect to external ram and program memory v ss 71 - ground : 0 v reference symbol pin i/o description
1999 jun 04 9 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL v cc(r) 72 - backup core power supply : 2.4 to 3.6 v only. separate from the core supply to allow a low capacity battery to be used to maintain the real-time clock (rtc) function. this should be powered from the main supply during normal operation and switched to battery backup when the main supply fails. dmcs 73 o external data memory select : external ram select pin, active low when the external data memory space is addressed. this output is driven from v cc(r) and v cc(b) supplies to ensure that the external ram is not enabled during power-down. pwrf ail 74 i power fail indicator : a low on this pin forces the embedded microcontroller into reset. reset will not be de-asserted until a set time after both pwrdn and pwrf ail go high. for correct start-up, this pin should be low on power-up. xtal4 75 o crystal 4 : output from the rtc oscillator ampli?er; this pin is only 3 v tolerant xtal3 76 i crystal 3 : input to inverting ampli?er used in the rtc oscillator circuits (32.768 khz); this pin is only 3 v tolerant pwrb 77 o backup supply select : this output is intended to drive an external fet used to switch the battery backup supply(s). it is active low and is controlled directly by the pwrf ail. pwrm 78 o main supply select : this output is intended to drive an external fet used to switch the main supply(s). it is active low and is controlled directly by pwrf ail. v ss 79 - ground : 0 v reference v cc(b) 80 - backup i/o power supply : 2.4 to 5.5 v only. supply for the ram select, power fail and power switching i/o pads only allowing these functions to be powered when the main power supply fails. this should be powered from the main supply during normal operation and switched to battery backup when the main supply fails. txd1 81 o transmitter output 1 : transmit channel for serial port 1 (uart1) of the embedded processor rxd1 82 i receiver input 1 : receive channel for serial port 1 (uart1) of the embedded processor. it is intended that this serial port is dedicated to differential gps information (dependent on ?rmware). txd0 83 o transmitter output 0 : transmit channel for serial port 0 (uart0) of the embedded processor. rxd0 84 i receiver input 0 : receive channel for serial port 0 (uart0) of the embedded processor. it is intended that this serial port is dedicated to the nmea data stream (dependent on ?rmware). v ss 85 - ground : 0 v reference v cc(p) 86 - main i/o power supply : 2.7 to 5.5 v operating range; main supply for the periphery in normal operation gpio4 87 i/o gpio bit 4 : standard general purpose i/o mapped into the segment 15 of the address space. the top 4 bits can be used as the xa external timer control access pins (t0, t1, t2 and t2ex). gpio3 88 i/o gpio bit 3 : standard general purpose i/o mapped into the segment 15 of the address space. the top 4 bits can be used as the xa external timer control access pins (t0, t1, t2 and t2ex). rfdat 89 o rfic set-up data : serial data output used to set up the uaa1570hl front-end ic. rfclk 90 o rfic set-up data : clock output for the serial data output used to set up the uaa1570hl front-end ic. the state of the rfdat and rfle lines is latched into the front-end ic on the rising edge. symbol pin i/o description
1999 jun 04 10 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL rfle 91 o rfic setup latch : output used to latch the rfic set-up into the active uaa1570hl control registers if2 92 i msb if input : msb of the 2-bit gps digital if signal input. clocked in on the rising edge of sclk. if only a 1-bit if input is available this input should be held high. if1 93 i lsb if input : lsb of the 2-bit gps digital if signal input. clocked in on the rising edge of sclk. gpio2 94 i/o gpio bit 2 : standard general purpose i/o mapped into the segment 15 of the address space. the top 4 bits can be used as the xa external timer control access pins (t0, t1, t2 and t2ex). gpio1 95 i/o gpio bit 1 : standard general purpose i/o mapped into the segment 15 of the address space. the top 4 bits can be used as the xa external timer control access pins (t0, t1, t2 and t2ex). gpio0 96 i/o gpio bit 0 : standard general purpose i/o mapped into the segment 15 of the address space. the top 4 bits can be used as the xa external timer control access pins (t0, t1, t2 and t2ex). n.c. 97 o not connected : do not connect rclk 98 i reference clock : input from the txco reference. not used internally. this is divided under ?rmware control to produce the sample clock, sclk, used to gate the if inputs. test1 99 i test pin : connect to pin 100 test2 100 o test pin : connect to pin 99 symbol pin i/o description
1999 jun 04 11 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.2 pin configuration. handbook, full pagewidth 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 77 76 v cc(b) v ss pwrm pwrb xtal3 xtal4 pwrfail dmcs v cc(r) v ss d0 d1 d2 d3 v cc(core) v ss d4 d5 d6 v cc(p) v ss d7 d8 d9 d10 d11 d12 d13 pwrdn v cc(p) sclk t1s tp3 tp4 gpio7 gpio6 gpio5 n.c. n.c. a19 a18 v cc(core) v ss xtal1 xtal2 v cc(p) v ss a17 a16 a15 a14 a13 a12 a11 v cc(p) test2 test1 rclk n.c. gpio0 gpio1 gpio2 if1 if2 rfle rfclk rfdat gpio3 gpio4 v cc(p) v ss rxd0 txd0 rxd1 txd1 v ss a7 a6 a5 a4 a3 v cc(p) v ss a2 a1 pmcs tp2 rstime tp1 wrh wrl rd d15 d14 v ss v ss a10 a9 a8 v cc(core) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SAA1575HL mhb461
1999 jun 04 12 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7 functional description 7.1 overview the function of the SAA1575HL is to accept any if data (1 or 2-bit) from a front-end rf ic (such as the uaa1570hl) and provide a serial nmea compatible gps position and time output. the if input is sampled synchronously with the front-end reference clock, sclk. data is decoded from the if input stream by one of eight parallel correlators which allow up to eight satellites to be tracked at one time. the acquisition, allocation and tracking of the satellites is performed under firmware control by the on-chip processor. in addition to the SAA1575HL and an appropriate front-end ic (such as the uaa1570hl), the only external components required to complete a functional gps receiver are some ram, the firmware rom and some discrete devices to control the power supplies. the need for external glue logic is eliminated by various chip-select functions implemented on the SAA1575HL. the SAA1575HL also contains an optional independent real-time clock (rtc) which requires a separate 32.768 khz crystal. this can be set to gps time by the processor and enables fast re-acquisition (a warm start) of satellites after power has been switched off. a separate supply pin is provided to allow the rtc to be powered while the rest of the ic is turned off. the block diagram of the SAA1575HL is shown in fig.1. the ic consists of a processor core, its associated peripherals, some internal memory and a series of gps correlators. the processor core is based on an embedded philips 80c51xa (known as the xa). the xa peripherals (uarts, timers, watchdog and general purpose i/os) are termed special function registers and are memory mapped in parallel with an area of the data memory. they are connected to the core by dedicated data and address buses. the internal data memory is also connected to the core by a dedicated bus. the rest of the ic (the correlators, rtc and system control) is mapped into the external data memory space. the multiplexed data and address buses provided by the xa core are separated by an on-chip latch to provide the distinct 16-bit data bus and 19-bit address bus. these are made available externally for connection to external memory via the external bus interface. the correlators, rtc and system control blocks are memory mapped into the highest page of the 16 pages in the xa data structure. both the rtc and the correlators are asynchronous to the system clock, with synchronization being achieved by firmware and interrupts. 7.2 the 80c51xa processor the microcontroller core in the SAA1575HL is a philips design called the xa (extended architecture) which is an extended 80c51-like 16-bit microcontroller. this is largely compatible with the 8051 but with various improvements. the main features of the xa compared to the 8051 can be summarized as follows: 16-bit versus 8-bit data processing 20-bit versus 16-bit address bus 3 clock instruction cycle versus 12 clock instruction cycle 10 mips versus 1 mips 20 cpu registers versus 1 accumulator all 20 cpu registers in the xa can be used as the accumulator register in the 8051 16 16 multiplication in 12 clocks, 32 16 division in 22 clocks new type of instructions such as normalization, sign extension and trap multi-tasking support versus no multi-tasking support. 7.3 the gps correlators the correlator block forms the gps specific hardware for correlating with the direct sequence spread spectrum gps signals. the 8 identical correlators share the 2-bit if input and the sample clock of the analog-to-digital converter (adc) of the front-end. the input signal is the 50 bits/s gps data spread by the 1.023 mbits/s pn code and modulated by the residual carrier. the residual carrier frequency is composed of the doppler frequency and the receiver local oscillator frequency offset. to recover the gps data and find the accurate timing of the received data for gps navigation from the low-level (as low as - 130 dbm) gps signal, the residual carrier frequency and phase have to be found by a phase-locked loop (pll) with minimum tracking phase error. the starting position of the pn code in the received signal is found by correlation within a delay-locked loop (dll). the channel correlator includes a local numerically controlled oscillator and a programmable local pn code generator with the phase rotation and correlation circuit.
1999 jun 04 13 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7.4 memory organization the memory space in the SAA1575HL is configured in a harvard architecture which means that the code and data memory are organized in separate address spaces. this section describes the SAA1575HL memory requirements. 7.4.1 d ata memory space the SAA1575HL contains 2 kbytes words of internal data memory. for correct firmware operation, a further 32 kbytes words of external data memory is needed with a maximum access time of 100 ns. the specifications of this external memory are firmware dependent. the figures given in this document are for the standard philips firmware. with other revisions of firmware the timings could differ by integer numbers of xtal1 clock cycles. in the SAA1575HL, all of the data read and write cycles are preceded by an internal arithmetic and logic elements (ales) cycle (as in any standard 80c51 system). the multiplexed address/data bus and the ale signal are not available externally. however, for clarity, these are illustrated in figs 3 to 6. fig.3 example of external data read (standard firmware). the timing is configurable under firmware control. handbook, full pagewidth mhb462 dmcs rd address bus address/ data ale internal signals xtal1 address external data address
1999 jun 04 14 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.4 example of external data write (standard firmware). the timing is configurable under firmware control. handbook, full pagewidth mhb463 dmcs wrh/wrl address bus address/ data ale internal signals xtal1 address external data address 7.4.2 c ode memory space the SAA1575HL has no internal code memory. the gps solution firmware resides in external memory. with the standard philips firmware, a rom with a maximum access time of 100 ns is required. the classic operation of a multiplexed address/data bus involves an address being set-up for every bus cycle. the internal ale signal is used to latch the address prior to the cycle on which the data is set-up. an example of the resulting timing is illustrated in fig.5. the SAA1575HL does not require an internal ale cycle for each code fetch. the lowest 3 address lines are not multiplexed with the data lines and so these can be used to incrementally read code locations. the xa core can therefore issue up to 8 word reads through sequential code memory for each ale cycle. this is termed a burst code read. an example of the resulting timing is illustrated in fig.6. any type of branch or jump in the program may require a code fetch in a non-sequential manner and a new ale cycle will be needed. this may occur at any stage in a code read. thus the length of the read strobe in a burst read is not necessarily an integer multiple of the individual code read length.
1999 jun 04 15 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.5 example of code read with ale (standard firmware). the timing is configurable under firmware control. handbook, full pagewidth mhb464 data bus pmcs address bus address/ data ale internal signals xtal1 address data input address fig.6 example of burst mode code read (standard firmware). the timing is configurable under firmware control. handbook, full pagewidth mhb465 data bus pmcs address bus address/ data ale internal signals xtal1 address 1 address 2 address 2 address 1 code word 2 code word 1
1999 jun 04 16 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7.5 cpu peripheral features the SAA1575HL contains the hardware for 3 timers, 2 uarts, a watchdog timer, a 3-bit rf ic programming link and an 8-bit general purpose i/o port. 7.5.1 t imers / counters the SAA1575HL has 2 standard 16-bit timer/counters and a third 16-bit up/down timer/counter. these timer/event counters can perform the following functions: measure time intervals and pulse duration count external interrupts generate interrupt requests generate pulse width modulation (pwm) or timed output waveforms. the timers are used by the standard philips firmware to generate the baud rates for the uart serial ports. the additional features are not used in the standard philips firmware but are available for use in custom firmware revisions. all of the timers are configured in the 16-bit auto-reload mode of operation. timer 1 is used to generate the baud rate for uart0 and timer 2 is used to generate the baud rate for uart1. in the standard philips firmware, timer 0 is not used. 7.5.2 w atchdog timer the watchdog timer protects the system from incorrect code execution by causing a processor reset if the watchdog timer underflows as a result of a failure of the firmware to feed the timer prior to it reaching its terminal count. in the standard philips firmware, the watchdog is enabled with a time-out period of 130 ms (at a clock frequency of 30 mhz). 7.5.3 uart s the SAA1575HL contains 2 uart ports, compatible with the enhanced uart modes 1 to 3 on the 8xc51fb (mode 0 operations not supported). with the exception of the removal of the mode 0 operation, the uarts in the SAA1575HL are identical to those in the xa-g3 product. each uart rate is determined by either a fixed division of the oscillator (in uart mode 2) or by one of the timer overflow rates (in uart modes 1 and 3). with the standard philips firmware, both uarts are configured to be in mode 1: variable rate 8-bit operation. ten bits are transmitted (via txdn) or received (via rxdn): a start bit, 8 data bits (lsb first), and a stop bit. in general, the uart clocks (which are 16 times the baud rate) are determined by the timer 1 or timer 2 overflow rate. with the standard philips firmware, timer 1 is used to generate the baud rate for uart0 and timer 2 is used to generate the baud rate for uart1. the baud rate is set to be 4800 bits/s for both uarts. 7.5.4 rf ic programming port the SAA1575HL is capable of programming the uaa1570hl via a standard 3-wire serial link. this consists of a clock line (sclk), data line (d15 to d0) and a latch enable (rfle). data is clocked into a holding register in the uaa1570hl serially on each rising edge of the output rfclk. once the complete serial packet has been clocked into the rf ic, the latch enable output, rfle, is asserted which copies the new word from the holding register in the rf ic into the control registers. proper timing of the clock, data and latch outputs is ensured by firmware. an example sequence is illustrated in fig.7. the signals shown would result in the value 1001 being loaded into the last 4 bits of the rf ic serial register. each loading operation of the rf ic reloads the complete rf control register. with the standard philips firmware, a 20-bit long word 0x5e320 is transmitted in this manner on start-up or re-initialization. this gives full compatibility with the philips uaa1570hl front-end ic. see the uaa1570hl for more details about the configuration options of the front-end ic.
1999 jun 04 17 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7.5.5 g eneral purpose i/o the SAA1575HL possesses an 8-bit general purpose i/o register and 8 associated i/os (see fig.8). with the standard philips firmware, all 8 of these pins are configured as outputs. with the standard philips firmware, only pin gpio0 is used. this is switched on at the end of the firmware initialization sequence and remains on subsequently. fig.7 example timing for uaa1570hl programming. x = dont care. handbook, full pagewidth mhb466 rfclk rfdat control holding rfle 1001 xxxx xx10 1001 xxx1 x100 xxxx fig.8 gpio pin drive circuits. handbook, full pagewidth mhb467 ion pull-up fet v cc(p) gpion pin clk en d data bus q write enable read enable cfgn 10 m a
1999 jun 04 18 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7.6 the real-time clock the real-time clock (rtc) is a functional unit used to generate time information. its purpose is to supply approximate gps time to the system firmware for the initial acquisition of satellites (a warm start). the power supply for the rtc is separate from the rest of the ic, allowing a low capacity battery to be used to maintain the low power rtc function. the timebase for the rtc should be provided by a dedicated 32.768 khz crystal which can be omitted if the rtc is not required. this is divided down by a fixed divider to provide the 1 hz timebase used for the rest of the rtc block. a digital sampling circuit is also included to prevent digital noise due to the on-chip processor causing incorrect timekeeping. the SAA1575HL uses a digital under-sampling system to ensure that ground bounce does not cause rtc timekeeping errors. this places a restriction on the ratio of xtal1 and xtal3 frequencies for which the rtc will operate correctly. this has been optimistic for the case f xtal1 = 30 mhz, f xtal3 = 32 khz and, assuming that the rtc crystal frequency will always be 32 khz, will operate correctly for the entire specified range of system frequencies. fig.9 real-time clock circuit. handbook, full pagewidth mhb468 32 khz oscillator xtal4 xtal3 xtal c c off-chip (optional) 32 khz sampler system clock 1 hz pre-scaler real-time clock counters
1999 jun 04 19 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7.7 the external bus the off-chip memories and the on-chip registers are on the same address and data bus. the routing of the data and address signals between the on-chip registers and the off-chip memories is controlled by a block known as the external bus interface. in addition, certain chip enable signals are decoded within the block to reduce the amount of external glue logic required in the complete system. the address latch, normally required on 80c51 systems, is implemented within the SAA1575HL. therefore, no ale signal is seen outside the ic and address and data lines are brought out on separate pins. however, since internally there is still the need to latch the address from a common address/data bus, signals on the data bus will be seen to change during the address set-up cycles. the lower 3 external address lines are driven directly by the xa core and are not latched. this allows burst code reads to be performed in which adjacent code locations are accessed without the need for an address latch cycle. signals similar to those used by a standard 80c51 or xa system are used to control the external bus activity. fig.10 SAA1575HL internal address and data routing. handbook, full pagewidth mhb469 address decoder le ale a4 to a19 d15 to d0 a3 to a1 address latch xa pmcs wrh, wrl, rd a3 to a1 d15 to d0 d15 to d0 to mmrs enable a4 to a19 a1 to a8 pmcs wrh, wrl, rd dmcs 16 16 3 3 16
1999 jun 04 20 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7.7.1 p rogram memory chip select this signal ( pmcs) is an active low strobe used to enable the output of the external code memory. it remains high when a read code is not in progress. 7.7.2 d ata memory chip select this signal ( dmcs) is an active low strobe used to enable the external data memory. the SAA1575HL hardware supports two distinct modes of operation of this signal (selected in firmware) designed for optimum power or optimum speed. the standard philips firmware is configured for optimum power. dmcs is taken low during an external data read or write operation to segments 0 to 14 of the memory map. to prevent the corruption of external data memory, the dmcs pin is driven on the backup supply voltage and will be held high once the pwrfail signal has been asserted low. with the standard philips firmware, the dmcs signal is gated by the external access read and write strobes. this should significantly reduce the power consumption of the external ram but may require the use of a slightly faster external memory (depending on clock speed and details of the external memory used). 7.7.3 r ead strobe this signal ( rd) is an active low strobe used to indicate that the xa is expecting data from the external bus. 7.7.4 w rite low byte strobe this signal ( wrl) is an active low strobe used to indicate that the xa is performing an external write. this strobe only applies to the lower data byte of the 16-bit data word, allowing byte writes to be performed from the 16-bit data. this strobe will also be taken low for word write operations. 7.7.5 w rite high byte strobe this signal ( wrh) is an active low strobe used to indicate that the xa is performing an external write. this strobe only applies to the higher data byte of the 16-bit data word, allowing byte writes to be performed from the 16-bit data. this strobe will also be taken low for word write operations. 7.8 backup supplies and reset the SAA1575HL is designed to operate correctly in situations when the main power supply fails. in addition to the main core and peripheral power supplies, separate pins are provided for backup core and peripheral supplies which enable critical (and low-power) functions to be maintained during the loss of main power. there is also an on-chip reset timer which will aid the design of a full power-down strategy. 7.8.1 s upply domains to allow for the use of inexpensive 5 v external components, the periphery of the SAA1575HL can be powered with a higher voltage than the core. therefore there is a distinction between the core and peripheral power supplies. in addition, there is the need to maintain certain functionality on a low-power supply in the event of main power failure. therefore there are 2 additional supplies required for so-called backup operation. thus there are four distinct power supply domains, two for the core supplies and two for the peripheral supplies. table 1 supply domains in normal operation, the backup core and pad supplies should be provided from the main power supply rather than a low-capacity battery since the power drawn on the backup supplies while the processor is operating may be significant. two output pins, pwrm and pwrb are provided to control this switching. supply description purpose v cc(core) main core supply (3 v) provides power for all core circuits, excluding those mentioned below v cc(p) main peripheral supply (3 to 5 v) provides power for all pins, excluding those mentioned below v cc(r) rtc core supply (2.4 to 3 v) powers the real-time clock, the 32 khz oscillator and the 32 khz de-bounce circuit; it also produces the signals for dmcs, pwrm and pwrb v cc(b) backup peripheral supply (2.4 to 5 v) provides power for the following pins: dmcs, pwrm, pwrb and pwrf ail
1999 jun 04 21 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL the power consumption of the SAA1575HL in the power-down mode is minimal since no outputs are changing. the only active circuit in power-down is the real-time clock. isolation between the power domains is controlled by the pwrfail input pin. this must be driven low in a power-failure situation to ensure that the backup domains are isolated from the main supply domains. if this is not done, it is possible that the registers contained in the backup supply domain will be corrupted as the main supply is cycled. it is also possible that under these circumstances a high backup supply current will be drawn (depending on details of the external supply circuitry). 7.8.2 p ower - down design strategy in power-down operation the main supplies are assumed to have failed. the backup core and pad supplies should be switched to backup power. the detection of the power failure and the power supply switching is the responsibility of the user. however, the SAA1575HL does provide several functions to aid this task. the power-down and power-fail operations of the SAA1575HL are controlled by two inputs, pwrdn and pwrfail, which are assumed to be connected to external voltage comparators. the use of external comparators allows the voltage thresholds to be set by the system designer. it also allows a certain amount of flexibility as to which supplies are monitored for power failure. 7.8.2.1 power-down control signals the power-down control signal pins (see table 2) are either inputs or outputs associated with the SAA1575HL power control. the descriptions are for the intended use of the control signals in a normal application. for a correct reset to occur, it is important that pwrfail should be held low as long as minimum voltages have been established on all four of the power supply domains. if this is not done various serious consequences may occur, including main oscillator failure, a high supply current state, a processor crash or rtc register corruption. table 2 power-down control signals signal function pwrdn power-down indicator : this should be driven low by an external comparator to indicate impending power failure. internally it sends an interrupt to the processor used to initiate a power-fail routine. at the end of this routine the standard ?rmware forces the processor into reset. this also inhibits the external ram chip select. reset is only de-asserted a set time after both pwrdn and pwrf ail go high, controlled by the rstime input. pwrf ail power fail indicator : this should be driven low by an external comparator to indicate immediate power failure. internally it forces immediate reset of the processor, isolation of the rtc and inhibition of the external ram chip select. it also controls the power switch outputs pwrb and pwrm. reset is only de-asserted a set time after both go high, controlled by the rstime input. rstime reset timer control : this sets the time delay between de-assertion of both pwrdn and pwrf ail and the de-assertion of the processor reset. if high, the delay is approximately 10 ms. if low the delay is approximately 10 m s. dmcs external ram chip select : this is driven via the backup supplied core and pads. in power-down this is isolated from the rest of the ic and the output held high to prevent corruption of the external ram. pwrm main power supply control : in normal operation this is held low. this can be used to switch the main supplies to all of the supply input pins. in normal operation the backup pad supply pin should be driven by the main supply and the backup core supply pins should be driven by the main core supply. when the ic goes into power-down mode this output goes high. in power-down the backup supply pins should be driven by their appropriate supplies. pwrb backup power supply control : this is the inverse of pwrm
1999 jun 04 22 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7.8.2.2 example of strategy for slow supplies the ultimate use of the power control signals is up to the user. however, two possibilities are presented as design examples. the first example will operate correctly in circuits where the rise times of the power supplies is slow compared to any delay between the supplies to the peripheral and core power domains. in this example, both the pwrdn and pwrfail logic inputs to the SAA1575HL are derived by comparing the v cc(p) supply voltage against known references. in general, since it is a lower voltage, the v cc(core) supply may hold and reach its nominal voltage quicker than the v cc(p) supply. as v cc(p) falls, the first threshold is reached and pwrdn is taken low. this triggers an interrupt in the firmware which is used to perform any required housekeeping. it is assumed that there is time for this to be completed before complete supply failure. at the end of the interrupt routine, the firmware places the SAA1575HL into reset. as v cc(p) continues to fall, the second threshold is reached and is taken low. this toggles the power controls, both pwrm and pwrb, and will force a reset if it has not already occurred. on power-up, the power controls both pwrm and pwrb will be switched once the second threshold voltage is reached. as the supply voltage rises further, the first voltage threshold will be reached at which time both pwrdn and pwrfail will be high. this starts the reset counter and the SAA1575HL will remain in reset until a set time after this, depending on the state of the input pin rstime. fig.11 example of power-down strategy with slow supplies. handbook, full pagewidth mhb470 pwrb delay while xa in interrupt routine reset timer delay set by rstime v t1 v cc(p) v cc(core) v t2 pwrfail pwrdn pwrm
1999 jun 04 23 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7.8.2.3 example of strategy for fast supplies the second example will operate correctly in circuits where the delay between the supplies to the peripheral and core power domains is significant compared to the rise times of the power supplies. this may occur in cases where the core supply is a regulated (delayed) version of the peripheral supply. if the previous strategy were used in this situation, it would be possible for the SAA1575HL to miss the pwrfail low state at power-up, resulting in the ic not being given a correct reset. in this example, the pwrdn logic input is derived as before by comparing the v cc(p) supply voltage against a known reference voltage. but in this instance the pwrfail logic input is derived by comparing the v cc(core) core supply against a threshold voltage. as v cc(p) falls, the first threshold level is reached and pwrdn is taken low. this triggers an interrupt in the firmware which is used to perform any required housekeeping. at the end of the interrupt routine, the firmware places the SAA1575HL into reset. however, if the fall times on the supplies is fast, it is likely that the pwrfail input will go low before the interrupt routine has been completed. this would force the SAA1575HL into immediate reset. at this time both pwrm and pwrb toggle to switch backup supply sources. on power-up, the v cc(p) supply rises quickly. however, since this only controls an interrupt flag and the SAA1575HL is still held in reset by pwrfail, this has no effect. only once the v cc(core) supply rises will pwrfail be de-asserted. this can only occur once the v cc(core) voltage has reached the set threshold, and so there is no risk of the ic missing the reset pulse. the SAA1575HL will come out of reset a set time after this, depending on the state of the input pin rstime. fig.12 example of power-down strategy with fast supplies. handbook, full pagewidth mhb471 pwrb delay while xa in interrupt routine reset timer delay set by rstime v t1 v t3 v cc(p) v cc(core) pwrfail pwrdn pwrm
1999 jun 04 24 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7.8.3 s ystem reset control the SAA1575HL contains an internal timer and control logic to perform various system reset tasks. control of this logic is by three external pins, pwrdn, pwrfail, and rstime. this allows the system designer to set the voltage thresholds at which the system goes into and comes out of reset. 7.8.3.1 the reset timer the heart of the reset system is a 20-bit counter with asynchronous reset, clocked from the xtal1 system clock. the reset counter is asynchronously reset if the pwrfail pin is low. once reset, the counter will only be enabled once both pwrfail and pwrdn go high. this prevents the SAA1575HL from leaving the reset state until both power detect inputs have flagged the power system as healthy. the internal reset signal is generated by decoding the reset counter. the decode value, and hence the time delay, is controlled by the reset time control pin, rstime. table 3 reset time control the internal reset is de-asserted a given number of xtal1 clock cycles after pwrfail and pwrdown go high. it is suggested that for most applications rstime should be held high, giving a reset time of approximately 10 ms. this would be needed to allow the on-chip oscillator to stabilize after power-up. the shorter reset time can be used for applications using an external xtal1 clock signal which does not need a long stabilization period. it is important that pwrfail should be low during power-up of the ic to give the correct reset. rstime input number of cycles before reset de-asserted time delay (f xtal1 = 30 mhz) 1 294 912 9.8 ms 0 288 9.6 m s 7.8.3.2 overall reset operation the assertion of the reset signal (by means already described) will cause the following to occur: internal xa processor reset internal registers reset data bus pins set to be inputs read and write strobes de-asserted gpio pins set to be inputs on-chip xtal1 oscillator enabled. 7.8.3.3 cpu reset operation assuming that the correct external pwrfail sequence is generated on power-up, the internal xa will receive the correct reset signal from the on-chip reset block. if the proper pwrfail is not performed, the operation of the on-chip reset block cannot be guaranteed and the xa may fail wholly or in part. the embedded xa requires a minimum length of reset to complete the various tasks. this minimum length is guaranteed by the on-chip reset block. the only restriction on the length of the pulse is that is should be long enough to be asynchronously detected by the SAA1575HL (typically 10 ns). the embedded cpu can also be reset by the watchdog timer (this may be disabled on some custom firmware revisions). 7.8.4 p ower saving modes the SAA1575HL supports two power saving modes; idle mode and sleep mode. both modes are selected by firmware (or message over the serial link if included in the firmware). in addition, the input to any of the correlators can be inhibited individually (by firmware) which will reduce the power consumed by the block to only the clock tree dissipation.
1999 jun 04 25 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7.8.4.1 sleep mode the sleep mode is intended to overlay the function of the standard 80c51xa idle mode. sleep is initiated by a firmware or external serial link command. this initiates a firmware routine which performs the following: 1. send serial command to power-down rf ic (uaa1570hl) 2. inhibit rclk, if2 and if1 inputs to SAA1575HL 3. enter standard 80c51xa idle state. in sleep mode the rclk and if inputs are prevented from entering the ic. this capability is included to cover the situation in which the SAA1575HL is used with a front-end which does not respond to the power-down command in a similar way to the uaa1570hl. sleep mode can be exited by any active hardware interrupt, for example a uart interrupt. the sleep mode has no effect on the operation of the rtc. 7.8.4.2 idle mode the idle mode is initiated by a firmware or external serial link command. this is a direct use of the standard 80c51xa idle mode. the interrupt signals from the active peripherals such as uarts, timers, host interface and external interrupts will cause the cpu to resume execution from the point at which it was halted. in the idle mode, all of the output pins retain their logic states from their pre-idle position. no other action is taken on entering idle mode. in particular, the correlators will remain active since rclk, if1 and if2 will not be prevented from entering the ic. 7.9 clock signals and oscillators the SAA1575HL requires 3 clock signals for full operation: xtal1: processor (system) clock xtal3: real-time clock crystal frequency (optional) rclk: gps reference clock. two of these clocks, xtal1 and xtal3, can be generated by on-chip oscillator circuits. the third, rclk, must be supplied from an external source; in most applications a temperature compensated oscillator module. 7.9.1 s ystem clock (xtal1) the SAA1575HL requires a system clock for the on-chip processor and related peripheral blocks. this can be provided from an external clock source via the xtal1 input pin or by using the on-chip oscillator circuit with an external resonating element connected between the xtal1 and xtal2 pins. in most circumstances this would be an external crystal accompanied by two capacitors connected to ground, a series resistor (to optimize power consumption) and a shunt resistor to ensure start-up under all conditions. optimum values of c, r p and r s will depend on the crystal used. however, typical values would be c = 20 pf, r p =1m w and r s = 200 w . the hardware places a restriction on the range of frequencies for which correct operation will occur; 26 mhz < f xtal1 < 32 mhz. however, the restriction on operating frequency imposed by the firmware is tighter than this. the standard philips firmware has been written on the assumption of a 30 mhz system clock frequency. fig.13 system clock oscillator circuit. handbook, halfpage mhb472 oscillator xtal2 xtal1 xtal c c off-chip on-chip r p (optional) r s (optional) system clock
1999 jun 04 26 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 7.9.2 rtc clock (xtal3) if the on-chip real-time clock is required (as with the standard philips firmware), a low frequency clock signal is required to run the clock. the SAA1575HL is designed so that a standard 32.768 khz watch crystal can be used for this purpose. since this is much slower than the system clock, a much lower power is required to run just the real-time clock, allowing it to be powered from a low-capacity battery when the main power supply fails. as with the system clock, there is an on-chip oscillator so that only a few passive external components are required. these would be an external crystal accompanied by two capacitors connected to ground, a series resistor (optional) and a shunt resistor to ensure start-up under all conditions. optimum values of c and r p will depend on the crystal used. however, typical values would be c = 22 pf and r p =1m w . 7.9.3 r eference clock (rclk) the reference clock input, rclk, is used as the source for the sampling of the if input signal. a divided-down version of rclk is output on the sample clock pin, sclk, for use by the front-end ic. the division ratio of rclk/sclk is programmable in firmware. in the standard philips firmware this ratio is set to 3. fig.14 rtc clock oscillator circuit. handbook, halfpage mhb473 oscillator xtal4 xtal3 xtal c c r p (optional) rtc clock off-chip on-chip
1999 jun 04 27 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 8 limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. human body model: c = 100 pf; r = 1.5 k w . 2. machine model: c = 200 pf; l = 0.75 m h; r = 0 w . 9 thermal characteristics symbol parameter conditions min. max. unit v cc(core) core supply voltage - 0.5 +3.6 v v cc(r) rtc core supply voltage - 0.5 +3.6 v v cc(p) peripheral dc supply voltage - 0.5 +5.5 v v cc(b) backup peripheral dc supply voltage - 0.5 +5.5 v d v cc absolute voltage differences between two v cc pins - 550 mv p tot total power dissipation - 500 mw t stg storage temperature - 65 +150 c t j junction temperature - 150 c t amb ambient temperature v cc(core) =v cc(r) = 3.3 v; v cc(p) =v cc(b) = 5.0 v - 40 +85 c v es electrostatic handling note 1 2000 - v note 2 200 - v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 45 k/w
1999 jun 04 28 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 10 dc characteristics v cc(p) =v cc(b) =5v; v cc(core) =v cc(r) =3v; t amb =20 c; f osc = 30 mhz; standard philips ?rmware (release hd00); note 1; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v cc(core) core supply voltage 2.7 3.3 3.6 v v cc(p) peripheral supply voltage 2.7 5.0 5.5 v v cc(r) rtc core supply voltage 2.4 3.3 3.6 v v cc(b) backup peripheral supply voltage 2.7 5.0 5.5 v i cc(core) core supply current normal mode - 35 - ma idle mode - 15 - ma sleep mode -- 10 m a i cc(p) peripheral supply current normal mode; note 2 - 20 - ma idle mode -- 1ma sleep mode -- 1ma i cc(r) rtc core supply current normal mode; note 3 - 10 30 m a idle mode; note 3 - 10 30 m a sleep mode; note 3 - 10 30 m a i cc(b) backup peripheral supply current normal mode; note 2 - 5 - ma idle mode - 1 -m a sleep mode - 1 -m a inputs: pins pwrf ail, pwrdn, rstime, rxd1, rxd0, if2, if1, rclk, test1, tp1, tp2, tp3 and tp4 v il low-level input voltage -- 1.5 v v ih high-level input voltage 3.5 -- v outputs (low drive current): pins pwrb, pwrm, t1s, rfclk, rfdat, rfle and test2 v ol low-level output voltage i ol = 2.0 ma -- 0.4 v v oh high-level output voltage i oh = 0.5 ma 2.4 -- v i drive(max) maximum drive current -- 2ma c l(max) maximum load capacitance -- 50 pf t d(t) transition delay c l =5pf - 7.4 - ns c l =25pf - 8.8 - ns outputs (high drive current): pins a19 to a1, dmcs, pmcs, txd0, txd1 and sclk v ol low-level output voltage i ol = 4.0 ma -- 0.4 v v oh high-level output voltage i oh = 1.0 ma 2.4 -- v i drive(max) maximum drive current -- 4ma c l(max) maximum load capacitance -- 100 pf t d(t) transition delay c l =10pf - 6.8 - ns c l =50pf - 8.1 - ns
1999 jun 04 29 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL notes 1. xtal1, xtal2, xtal3 and xtal4 are not specified with respect to levels. 2. depends on all the external circuit driven by outputs. 3. specified at rtc clock frequency of 32.768 khz. i/o: pins wrl, wrh and rd v il low-level input voltage -- 1.5 v v ih high-level input voltage 3.5 -- v v ol low-level output voltage i ol = 4.0 ma -- 0.4 v v oh high-level output voltage i oh = 1.0 ma 2.4 -- v i drive(max) maximum drive current -- 4ma c l(max) maximum load capacitance -- 100 pf t d(t) transition delay c l =10pf - 7.0 - ns c l =50pf - 8.7 - ns i/o (pull-up): pins d15 to d0 and gpio7 to gpio0 v il low-level input voltage -- 1.5 v v ih high-level input voltage 3.5 -- v v ol low-level output voltage i ol = 4.0 ma -- 0.4 v v oh high-level output voltage i oh = 1.0 ma 2.4 -- v i drive(max) maximum drive current -- 4ma c l(max) maximum load capacitance -- 100 pf t d(t) transition delay c l =10pf - 8.9 - ns c l =50pf - 11.0 - ns i pu pull-up current - 10 -m a symbol parameter conditions min. typ. max. unit
1999 jun 04 30 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 11 ac characteristics v cc(p) =v cc(b) =5v; v cc(core) =v cc(r) =3v; t amb =20 c; f osc = 30 mhz; standard philips ?rmware (release hd00); unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit external clock f osc oscillator frequency 26 30 32 mhz t clk clock period and cpu timing cycle - 33.3 - ns t clkh clock high time 40 to 60% duty cycle - 6.7 - ns t clkl clock low time 40 to 60% duty cycle - 6.7 - ns t r(clk) clock rise time - 5 - ns t f(clk) clock fall time - 5 - ns f clk(ref) reference clock frequency - 14.4 35 mhz external program memory read (non-burst code read); see fig.16 t avau address valid time period 163.7 165.7 - ns t avpl address valid to pmcs asserted 62.7 65.7 - ns t w(pmcs) pmcs pulse width 97.0 98.0 - ns t pliv pmcs low to instruction valid - 82.0 85.0 ns t h(i) instruction hold time after pmcs de-asserted 0.0 -- ns t aviv address valid to instruction valid (access time) - 148.7 151.7 ns t su(i) instruction set-up time before pmcs de-asserted 14.0 16.0 - ns t pxiz bus 3-state after pmcs de-asserted - 30.0 36.0 ns t h hold time of a (3 : 1) after pmcs de-asserted 0.0 1.0 - ns external program memory read (burst code read); see figs 16 and 17 t avau address valid time period 131.3 132.3 - ns t aviv address valid to instruction valid (access time) - 115.3 118.3 ns t ivau instruction valid to address unde?ned 15.0 17.0 - ns t auiu address valid to instruction unde?ned 0.0 -- ns external data memory read; see fig.18 t avau address valid time period 163.7 164.7 - ns t rlel rd asserted to dmcs asserted note 1 - 2.0 4.0 ns t w(dmcs) dmcs pulse width 97.0 98.0 - ns t rheh rd de-asserted to dmcs de-asserted - 2.0 6.0 ns t avrl address valid to rd asserted 64.7 65.7 - ns t w(rd) rd pulse width 98.0 -- ns t avdv address valid to data valid (access time) - 148.7 151.7 ns t rldv rd asserted to data valid - 82.0 85.0 ns t su(d) data set-up time before rd de-asserted 15.0 16.0 - ns t h(d) data hold time after rd de-asserted 0.0 -- ns t rhdz bus 3-state after rd de-asserted - 30.0 36.0 ns
1999 jun 04 31 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL notes 1. for default dcms operation. 2. the 1 s pulse output is only valid when at least one channel is locked. table 4 explanation of symbol characters in chapter ac characteristics external data memory write; see fig.19 t avau address valid time 164.7 -- ns t wldl wrh and wrl asserted to dmcs asserted note 1 - 2.0 4.0 ns t w(dmcs) dmcs pulse width 65.7 -- ns t whdh wrh and wrl de-asserted to dmcs de-asserted - 2.0 4.0 ns t avwl address valid to wrh and wrl asserted 63.7 -- ns t wlwh wrh and wrl pulse width 64.7 65.7 - ns t avqv address valid to data valid 67.7 -- ns t qvwl data valid to wrh and wrl de-asserted - 9.0 - 4.0 - ns t whau wrh and wrl de-asserted to address unde?ned 2.0 -- ns t h(d) data hold time after wrh and wrl de-asserted 0 1.0 - ns gps if input timing; see fig.20 t fvsh if set-up time before rising edge of sclk - 10 - ns t shfv if hold time after rising edge of sclk 0 -- ns 1 second pulse output; see fig.21 t w(t1s) t1s pulse width - 1.0 -m s t t1s t1s pulse period note 2 - 1.0 - s symbol character description a address c clock d input data e dmcs strobe i instruction (program memory) p pcms strobe q output data r rd w wrh or wrl strobes h logic high l logic low u unde?ned v valid z high impedance or pull-up symbol parameter conditions min. typ. max. unit
1999 jun 04 32 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.15 external xtal1 clock drive. handbook, full pagewidth mhb474 xtal1 t chcl t clch 4.5 v 0.45 v 3.5 v 0.9 v t clkl t clkh fig.16 external program memory read cycle (non-burst). handbook, full pagewidth mhb475 d15 to d0 pmcs a19 to a1 2.4 v 0.4 v t aviv t avau 2.4 v 0.4 v 2.4 v 0.4 v 0.4 v t avpl t w(pmcs) t su(l) t h(l) t pliv t pxiz t h 2.4 v 0.4 v
1999 jun 04 33 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.17 external program memory read cycle (burst). handbook, full pagewidth mhb476 t ivau t auiu 2.4 v 0.4 v t avau t aviv 2.4 v 0.4 v d15 to d0 pmcs a19 to a1 fig.18 external data memory read cycle. default dmcs operation. handbook, full pagewidth mhb477 rd d15 to d0 dmcs a19 to a1 2.4 v 0.4 v t avdv t w(dmcs) t rlel 2.4 v t avau 0.4 v 2.4 v 2.4 v 0.4 v 0.4 v t avrl t w(rd) t su(d) t rldv t rhdz t rheh 2.4 v 0.4 v data in t h(d)
1999 jun 04 34 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.19 external data memory write cycle. default dmcs operation. handbook, full pagewidth mhb478 wrh or wrl d15 to d0 dmcs a19 to a1 2.4 v 0.4 v t avqv t w(dmcs) t wldl 2.4 v t avau 0.4 v 2.4 v 2.4 v 0.4 v 0.4 v t avwl t wlwh t qvwl t whdh t h(d) t whau 2.4 v 0.4 v data out fig.20 if input timing. handbook, full pagewidth mhb479 if1, if2 sclk t fvsh t shfv 2.4 v 0.4 v 2.4 v
1999 jun 04 35 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 12 default application and demonstration board fig.21 t1s output pulse timing. signal may be inverted under firmware control. handbook, full pagewidth mhb480 t1s t w(t1s) 2.4 v 0.4 v 0.4 v t t1s fig.22 overall schematic. handbook, full pagewidth mhb289 digital processor rclk sclk sign rfdata rfclk rfle rf front-end rclk sclk sign rfdata power supply vrtc v bb batt_on batt_off vrtc v bb batt_on batt_off rfclk rfle
1999 jun 04 36 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.23 baseband circuitry (continued in fig.24). mhb290 handbook, full pagewidth 44 73 47 46 45 41 40 74 14 15 52 76 wrl wrh a1 tp1 pmcs dmcs rd 39 35 34 33 32 36 29 28 a6 a7 a8 a9 a2 a3 a4 a5 27 a10 24 22 21 20 19 23 18 11 a15 a16 a17 a18 a11 a12 a13 a14 10 a19 70 68 67 64 63 69 62 59 d4 d5 d6 d7 d0 d1 d2 d3 58 d8 57 55 54 53 56 d13 d9 d10 d11 d12 49 48 d14 d15 89 rfdat 90 91 rfclk rfle 16 25 37 51 61 86 v cc(p) v cc(p) v cc(p) v cc(p) v cc(p) v cc(p) v cc1 v cc2 v cc3 v cc4 v cc5 v cc6 12 30 66 v cc(core) v cc(core) v cc(core) v dd1 v dd2 v dd3 72 80 v cc(b) v cc(r) vrtc1 v bb1 xtal2 xtal3 pwrfail pwrdn xtal1 75 83 84 81 82 4 txd1 rxd1 tp4 xtal4 txd0 rxd0 42 96 95 94 gpio1 gpio2 tp2 gpio0 88 87 5 6 gpio7 gpio6 gpio3 gpio4 7 gpio5 8 9 n.c. n.c. u204 SAA1575HL r207 470 w r206 10 k w d201 bas16 rclk sclk sign batt_on batt_off rclk sclk sign batt_on batt_off v cc v cc v cc v cc r205 10 k w r204 1 m w v cc 10 pf c207 c208 180 w r203 v cc v cc 1 jp202 header 10 2 3 4 5 6 7 9 8 10 10 pf jp201 jmp3 tp218 tp216 tp225 tp219 tp220 tp221 tp211 tp210 tp209 tp208 98 1 rclk sclk tp201 tp202 93 92 3 if1 if2 tp3 tp203 2 t1s tp204 v cc v cc 77 78 43 rstime pwrb pwrm sign t1s_out batt_on batt_off 13 v ss 17 v ss 26 v ss 31 v ss 38 v ss 50 v ss 60 v ss 65 v ss 71 v ss 79 v ss 85 v ss tp205 tp206 97 99 100 test1 test2 n.c. tp207 tp222 tp223 tp224 1 23 v cc out gnd u207 zm33164 tp217 tp229 1 23 v cc out gnd u206 zm33064 c209 10 m f (6.3 v) y201 30 mhz r202 10 m w 27 pf c205 c206 0 w r201 27 pf tp212 tp213 tp214 tp215 tp230 y202 32.678 khz gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v cc c224 33 nf c223 33 nf c222 33 nf c221 33 nf v cc6 c220 33 nf v cc5 c219 33 nf v cc4 c218 33 nf v cc3 c217 33 nf v cc2 c216 33 nf v cc1 c215 33 nf vrtc1 c214 33 nf v bb1 c213 33 nf v dd3 c212 33 nf v dd2 c211 33 nf v dd1 c210 33 nf gnd
1999 jun 04 37 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.24 baseband circuitry (continued from fig.23). mhb291 handbook, full pagewidth r224 220 w r210 open r223 220 w r209 open r222 220 w r208 open rfle rfclk rfdata rfle rfclk rfdata rfl rfc rfd tp227 tp226 tp228 gnd v cc1 v cc v cc2 v cc3 v cc4 v cc5 v cc6 c225 47 m f (6.3 v) 1 w r216 v dd1 v dd v dd2 v dd3 vrtc1 v bb1 c226 47 m f (6.3 v) 1 w r213 vrtc 1 w r212 v bb 1 w r211 gnd gnd 11 13 15 16 17 12 18 19 10 8 7 6 5 9 4 3 d4 d5 d6 d7 d0 d1 d2 d3 d12 d13 d14 d15 d8 d9 d10 d11 a5 a6 a7 a8 a1 a2 a3 a4 a4 a5 a6 a7 a0 a1 a2 a3 25 21 23 2 26 24 1 20 a13 a14 a15 /dmcs a9 a10 a11 a12 a12 a13 a14 /ce a8 a9 a10 a11 22 /rd /oe 28 v bb 14 gnd 27 /wrh /we u202 m5m5256bvp 11 13 15 16 17 12 18 19 10 8 7 6 5 9 4 3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 a5 a6 a7 a8 a1 a2 a3 a4 a4 a5 a6 a7 a0 a1 a2 a3 25 21 23 2 26 24 1 20 a13 a14 a15 /dmcs a9 a10 a11 a12 a12 a13 a14 /ce a8 a9 a10 a11 22 /rd /oe 27 /wrl /we u203 m5m5256bvp 21 19 18 17 16 20 15 14 24 26 27 28 29 25 30 31 d4 d5 d6 d7 d0 d1 d2 d3 11 9 8 7 6 10 5 4 d13 d14 d15 d16 d8 d9 d11 d12 2 43 v pp v cc v cc /pgm a5 a6 a7 a8 a1 a2 a3 a4 a4 a5 a6 a7 a0 a1 a2 a3 32 36 37 38 39 35 40 a13 a14 a15 a9 a10 a11 a12 a12 a13 a14 a8 a9 a10 a11 41 42 44 a16 a17 a15 a16 3 /ce 22 /pmcs /oe u205 27c202 gnd 13 7 6 20 21 17 8 5 12 15 16 2 3 14 1 28 /t3in /t4in r1out r2out v + v - /t1in /t2in rxd0 rxd1 txd0 txd1 26 22 19 24 25 r4out r5out en /shdn r3out t1out t2out t3out t4out c1 + c1 - c2 + c2 - 9 27 23 18 4 /r5in /r1in /r2in /r3in /r4in u201 j201 db9 db9 j202 max213eai v cc v cc v cc v cc 3 7 2 6 1 5 9 4 8 3 7 2 6 1 5 9 4 8 c203 100 nf (50 v) c204 100 nf (50 v) 100 nf (50 v) 100 nf (50 v) c202 c201 gnd gnd 28 v bb 14 gnd 12 34 gnd
1999 jun 04 38 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.25 rf front-end circuit (continued in fig.26). mhb292 handbook, full pagewidth r315 2.7 k w r314 2.7 k w r313 6.8 k w r320 2.21 k w r321 2.21 k w c346 33 nf c333 33 nf v cc v cca c344 10 nf (50 v) c339 4.7 pf c340 150 pf c341 3.9 nf c342 4700 pf c337 33 nf c336 33 nf c335 33 nf c338 15 pf c348 10 pf c343 4700 pf vrf vrf vrf vrf l305 6.8 nh r326 10 k w r327 10 k w r319 20 k w r316 10 k w r312 3.9 k w r318 10 k w r317 10 k w 5 4 5 6 7 8 1 2 3 8 39 12 10 32 40 7 8 14 6 x301 tco-987q - + 2 1 3 d301 smv1233-004 rfdata 7 rfclk 23 rfle 34 sign r310 18 w r311 18 w 37 30 29 28 27 c334 33 nf r309 open r325 1 w c347 open c330 33 nf 1 36 31 33 c332 33 nf c329 33 nf 19 16 c331 33 nf 9 41 43 sclk liminn bfcn v cca(lna1) v cca(lna2) v cca(pll) v cca(lim) v cca(mx2) v cca(mx1p) v cca(vco) p41gnd v ddd liminp sclk bfcp refin p39gnd comp p12gnd tank data clock strobe sign vrf v ddd v ccd rclk u302 max903esa dgnd agnd agnd agnd agnd agnd agnd dgnd agnd r322 r324 open 12 k w c345 1 m f (16 v) c308 open vrf m1biasp m1biasn l306 180 nh l307 180 nh r323 r304 0 w 2.21 k w vrf m2biasp m2biasn l308 27 m h l309 open agnd agnd agnd agnd agnd agnd agnd agnd uaa1570hl
1999 jun 04 39 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.26 rf front-end circuit (continued from fig.25). mhb293 handbook, full pagewidth r306 909 w r303 9 w r307 9 w c315 6.8 pf c316 6.8 pf c317 8.2 pf c318 8.2 pf c325 27 pf c328 33 nf (50 v) c327 10 pf (50 v) c324 1.5 pf c326 0.56 pf l303 330 nh l304 330 nh 45 lna1in 48 3 lna1out lna2in lna2out uaa1570hl vrf l = 367 mils (9.3 mm) w = 33 mils 50 w w = 6 mils 100 w c321 0.27 pf c307 open c305 open c323 2.2 pf l = 355 mils (9 mm) w = 6 mils 100 w l = 286 mils (7.3 mm) w = 6 mils 100 w l = 386 mils (10 mm) l = 1020 mils w = 8.8 mils l = 900 mils w = 8.8 mils l = 315 mils (8.1 mm) w = 6 mils 100 w j301 sma-f 1 25 346 bpf301 mf1012s-1 i/o i/o 6 14 mx1in 17 if1p m1biasp 18 if1n 21 if2inn 22 if2inp 24 if2p 25 if2n liminp liminn m1biasn m2biasp m2biasn c320 1.2 pf c313 36 pf c314 36 pf c319 39 pf r305 820 w r302 0 w 0 w r301 c302 47 pf c304 open c303 47 pf c312 1000 pf c311 1000 pf l301 22 m h l302 22 m h 44 lna1gnd1 46 biasgnd1 47 lna1gnd2 5 lna2gnd2 4 biasgnd2 2 lna2gnd1 42 p42gnd 38 pllgnd 26 limgnd 20 mx2gnd 13 mxpgnd 35 dgnd 15 mx1gnd 11 vcognd c301 82 pf c309 18 pf c310 68 pf c306 0.47 pf c322 2.2 pf l = 412 mils (10.5 mm) w = 6 mils 100 w l = 217 mils (5.5 mm) w = 33 mils 50 w 1 25 346 bpf302 mf1012s-1 i/o i/o dgnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd
1999 jun 04 40 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.27 power supply circuitry. handbook, full pagewidth mhb294 gnd v bat r117 1 k w b101 3 v 170 mah c114 22 m f (6.3 v) v103 bc858 v105 bc858 gnd gnd v cc v cc v bat r113 47 k w r109 470 w r110 1 m w r112 1 m w r115 10 m w batt_on batt_off v bb c113 22 m f (6.3 v) v104 bc858 v102 bc848 v101 bc848 v106 bc858 gnd gnd v dd v bat r114 47 k w r116 10 m w vrtc r111 1 m w c112 470 nf gnd u103 lp2951cm in 8 sd 3 6 vtap 2 snse 1 out fb 7 4 c105 100 nf tp103 v dd(in) v dd v cc c106 100 nf c111 10 m f (6.3 v) r106 18 k w r108 12 k w r103 1 w gnd gnd gnd gnd gnd gnd gnd 5 err u101 pl101 jmp3 in 2 out 3 adj 1 c101 1 nf d102 ll4007 tp101 v cc v cc d101 ll4007 c109 10 m f (10 v) c107 1 m f (20 v) c102 1 nf c108 22 m f (5 v) r118 270 w r119 820 w r101 1 w gnd gnd gnd gnd gnd gnd gnd u102 lm317t(3) lm317t(3) in 2 out 3 adj 1 3 v/5 v jp101 1 2 c103 1 nf d104 ll4007 tp102 vrf vrf d103 ll4007 c116 10 m f (10 v) c115 1 m f (20 v) c104 1 nf c110 22 m f (5 v) r120 240 w r121 390 w r122 330 w r102 1 w
1999 jun 04 41 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL the gps system application demonstration board consists of 6 layers with a total final thickness of 1.5 mm. the pcb material is fr4. fig.28 demonstration board top layer plus components (real size 88.9 mm 88.9 mm). mhb295 handbook, full pagewidth c326 bpf302 l303 * * d301 l304 r314 r316 r325 r309 r306 r319 r310 r311 r305 r301 c310 c303 r216 c220 r211 c213 r302 l305 l302 l301 c322 c311 c312 c301 u301 c325 c324 c314 c317 c305 c319 c302 c309 c341 jp202 c318 c334 c320 c338 c306 c327 c328 c329 pmcs wrh c217 dmcs pwrfail c211 wrl rd pwrdn ptest vrf in x301 rs232 #0 u204 c216 c213 c219 c215 c210 r206 pl101 c103 r120 r121 r102 c101 c107 c109 u101 r103 u102 c116 c115 r122 r303 r307 1 batt_off u201 r326 r327 u206 c209 r212 c212 gnd/v cc v cc in v dd in r118 + + r119 c102 r101 jp101 1 batt_on rxd1 txd1 txd0 rxd0 rfclk rfdata rfle sign dac rclk sclk t1s_out 1 c223 u205 3 v/170 mah r205 u207 r224 r210 r223 r209 r222 r208 r213 c214 rs232 #1 gps demo board version 1.3
1999 jun 04 42 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.29 demonstration board 2nd layer. mhb296 handbook, full pagewidth
1999 jun 04 43 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.30 demonstration board 3rd layer. mhb297 handbook, full pagewidth
1999 jun 04 44 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.31 demonstration board 4th layer. mhb298 handbook, full pagewidth
1999 jun 04 45 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.32 demonstration board 5th layer. mhb299 handbook, full pagewidth
1999 jun 04 46 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL fig.33 demonstration board bottom layer plus components. mhb300 handbook, full pagewidth c326 bpf302 l303 * * d301 l304 r314 r316 r325 r309 r306 r319 r310 r311 r305 r301 c310 c303 r216 c220 r211 c213 r302 l305 l302 l301 c322 c311 c312 c301 u301 c325 c324 c314 c317 c305 c319 c302 c309 c341 jp202 c318 c334 c320 c338 c306 c327 c328 c329 pmcs wrh c217 dmcs pwrfail c211 wrl rd pwrdn ptest vrf in x301 rs232 #0 u204 c216 c213 c219 c215 c210 r206 pl101 c103 r120 r121 r102 c101 c107 c109 u101 r103 u102 c116 c115 r122 r303 r307 1 batt_off u201 r326 r327 u206 c209 r212 c212 gnd/v cc v cc in v dd in r118 + + r119 c102 r101 jp101 1 batt_on rxd1 txd1 txd0 rxd0 rfclk rfdata rfle sign dac rclk sclk t1s_out 1 c223 u205 3 v/170 mah r205 u207 r224 r210 r223 r209 r222 r208 r213 c214 rs232 #1 gps demo board version 1.3
1999 jun 04 47 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL table 5 component list for gps demonstration board component type component characteristics value tolerance package b101 lithium battery 3 v/170 mah - cr1/3 c101 to c104, c311 and c312 ceramic capacitor 1 nf/50 v 10% 603 c105, c106, c201 to c204 ceramic capacitor 100 nf/50 v 20% 603 c107 and c115 ceramic capacitor 1 m f/63 v 20% 1210 c108 and c110 tantalum capacitor 22 m f/16 v 20% - c109 and c116 tantalum capacitor 10 m f/16 v 20% - c111 and c209 tantalum capacitor 10 m f/6.3 v 20% - c112 ceramic capacitor 470 nf/63 v 20% 1206 c113 and c114 tantalum capacitor 22 m f/6.3 v 20% - c205, c206 and c325 ceramic capacitor 27 pf/50 v 5% 603 c207, c208, c327 and c348 ceramic capacitor 10 pf/50 v 5% 603 c210 to c224, c328 to c337 and c346 ceramic capacitor 33 nf/63 v 10% 603 c225 and c226 tantalum capacitor 47 m f/6.3 v 20% - c301 ceramic capacitor 82 pf/50 v 5% 603 c302 and c303 ceramic capacitor 47 pf/50 v 5% 603 c304, c305, c307, c308 and c347 - not loaded -- c306 ceramic capacitor 0.47 pf/50 v 0.1 pf 603 c309 ceramic capacitor 18 pf/50 v 5% 603 c310 ceramic capacitor 68 pf/50 v 5% 603 c313 and c314 ceramic capacitor 36 pf/50 v 5% 603 c315 and c316 ceramic capacitor 6.8 pf/50 v 0.25 pf 603 c317 and c318 ceramic capacitor 8.2 pf/50 v 0.25 pf 603 c319 ceramic capacitor 39 pf/50 v 5% 603 c320 ceramic capacitor 1.2 pf/50 v 0.25 pf 603 c321 ceramic capacitor 0.27 pf/50 v 0.1 pf 603 c322 and c323 ceramic capacitor 2.2 pf/50 v 0.25 pf 603 c324 ceramic capacitor 1.5 pf/50 v 0.25 pf 603 c326 ceramic capacitor 0.56 pf/50 v 0.1 pf 603 c338 ceramic capacitor 15 pf/50 v 5% 603 c339 ceramic capacitor 4.7 pf/50 v 0.25 pf 603 c340 ceramic capacitor 150 pf/50 v 5% 603 c341 ceramic capacitor 3.9 nf/50 v 10% 603 c342 and c343 ceramic capacitor 4.7 nf/50 v 5% 603 c344 ceramic capacitor 10 nf/50 v 10% 603 c345 tantalum capacitor 1 m f/16 v 20% - d101 to d104 ll4007 diode, equivalent to 1n4007 --- d201 smd diode bas 16 -- sot23
1999 jun 04 48 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL d301 alpha smv1204-133 varactor -- sot23 l301 and l302 smd inductor 22 m h 5% 1008 l303 and l304 smd inductor 330 nh 5% 1008 l305 smd inductor 6.8 nh 5% 603 l306 and l307 smd inductor 180 nh 5% 1008 l308 smd inductor 27 m h 5% 1008 l309 - not loaded -- r101, r102, r103, r211, r212, r213, r216 and r325 smd resistor 1 w 5% 603 r106 smd resistor 18 k w 5% 603 r108 and r322 smd resistor 12 k w 1% 603 r109 and r207 smd resistor 470 w 1% 603 r110, r111, r112 and r204 smd resistor 1 m w 1% 603 r113 and r114 smd resistor 47 k w 1% 603 r115, r116 and r202 smd resistor 10 m w 1% 603 r117 smd resistor 1 k w 1% 603 r118 smd resistor 270 w 1% 603 r119 and r305 smd resistor 820 w 1% 603 r120 smd resistor 240 w 1% 603 r121 smd resistor 390 w 1% 603 r122 smd resistor 330 w 1% 603 r201, r301, r302 and r304 smd resistor 0 w- 603 r203 smd resistor 180 w 5% 603 r205, r206, r316, r317, r318, r326 and r327 smd resistor 10 k w 1% 603 r208, r209, r210, r309 and r324 - not loaded -- r222 to r224 smd resistor 220 w 5% 603 r303 and r307 smd resistor 9.1 w 5% 603 r306 smd resistor 910 w 1% 603 r310 and r311 smd resistor 18 w 1% 603 r312 smd resistor 3.9 k w 1% 603 r313 smd resistor 6.8 k w 1% 603 r314 and r315 smd resistor 2.7 k w 1% 603 r319 smd resistor 20 k w 5% 603 r320, r321 and r323 smd resistor 2.2 k w 1% 603 u101 and u102 (1) lm317t voltage regulator -- to220 u103 lp2951cm voltage regulator (national) -- so8 component type component characteristics value tolerance package
1999 jun 04 49 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL note 1. with heat sink depending on input voltage. u201 max213eairs2312 transceiver (maxim) -- ssop28 u202 and u203 sram m5m5256bfp-70ll 32k 8 (mitsubishi) -- so28 u205 27c202 eprom -- plcc44 u206 zm33064 power monitor --- u207 zm33164 power monitor --- u302 max903esa comparator (maxim) -- so8 v101 and v102 bc848 or bc847c npn transistor -- sot23 v103 to v106 bc858 pnp transistor -- sot23 x301 tcxo tco-987q --- y201 30 mhz crystal, 16 pf load capacitance --- y202 smd crystal 32.768 khz 30 ppm - bpf301 and bpf302 mf1012s-1 saw ?lter --- component type component characteristics value tolerance package
1999 jun 04 50 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 13 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.20 0.05 1.5 1.3 0.25 0.28 0.16 0.18 0.12 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.12 0.1 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 95-12-19 97-08-04 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e q e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1
1999 jun 04 51 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 14 soldering 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 14.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1999 jun 04 52 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL 14.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 15 definitions 16 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1999 jun 04 53 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL notes
1999 jun 04 54 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL notes
1999 jun 04 55 philips semiconductors product speci?cation global positioning system (gps) baseband processor SAA1575HL notes
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 1999 65 philips semiconductors C a worldwide company netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero 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philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy printed in the netherlands 285002/02/pp56 date of release: 1999 jun 04 document order number: 9397 750 06055

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